Freescale Semiconductor /MKL05Z4 /SIM /SOPT5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SOPT5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)UART0TXSRC 0 (0)UART0RXSRC 0 (0)UART0ODE

UART0RXSRC=0, UART0TXSRC=0, UART0ODE=0

Description

System Options Register 5

Fields

UART0TXSRC

UART0 transmit data source select

0 (0): UART0_TX pin

1 (1): UART0_TX pin modulated with TPM1 channel 0 output

UART0RXSRC

UART0 receive data source select

0 (0): UART0_RX pin

1 (1): CMP0 output

UART0ODE

UART0 Open Drain Enable

0 (0): Open drain is disabled on UART0

1 (1): Open drain is enabled on UART0

Links

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